Implementation of FPGA Architecture for OFDM-SDR with an optimized Direct Digital Frequency Synthesizer

A Software Defined Radio (SDR) is defined as a radio in which the receive digitization is performed at some stage downstream from the antenna, typically after wideband filtering, low noise amplification, and down conversion to a lower frequency in subsequent stages with a reverse process occurring for the transmit digitization. In an SDR, Digital Signal Processing in flexible and reconfigurable functional blocks define the characteristics of the radio. Researchers in the area of Communication and VLSI have a growing tendency to develop state-of-the-art architectures for SDR. The backbone of SDR framework in the digital domain is a direct digital frequency synthesizer (DDFS). Using DDFS, we can generate the high frequency carrier waves in digital domain and modulate the message on it. The optimization of the DDFS includes Lookup Table based designs and Coordinate Rotation Digital Computer (CORDIC) based designs. Lookup Table based designs require huge ROMs for implementation and are declared to be area-hungry. On the other hand, CORDIC based techniques use iterative algorithms for the computation of Sine and Cosine functions and are computationally inefficient. Each sample of Sine and Cosine requires 4 multiplications and 2 additions. However, the design in “The Proposed Architecture for DDFS” is even simpler and faster. It utilizes 2 adders and 2 multipliers to generate a sample of sine and cosine. This design is more area and time efficient than CORDIC and look-up table based approaches. The main objective of This paper presents the framework for hardware implementation of SDR using Orthogonal Frequency Division Multiplexing (OFDM). The framework comprises of VLSI mapping of algorithms, Orthogonal Frequency Division Multiplexing (OFDM), 8 Phase Shift Keying (8PSK), Fast Fourier Transform (FFT) Algorithms and most importantly, the algorithm for Direct Digital Frequency Synthesis (DDFS). A digital frequency synthesizer with optimized time and area resources has been proposed for the SDR. This VLSI implementation of the DDFS computes the sine and cosine function on a single edge of clock, thus proving to be optimized in terms of area and speed. In this design I want to use Verilog HDL as a description language for mapping Algorithms in VLSI. Xilinx Spartan 3 XC3S200 Field Programmable Gate Array(FPGA) was chosen as a Hardware Platform for the System Implementation. Keywords— Software Defined Radio, Direct Digital Frequency Synthesis, Orthogonal Frequency Division